£375k European Commission Grant for 3-D circuit research
A Lancaster University academic has been awarded £374k by the European Commission to carry out research into 3-D Integration of electronic circuits.
Dr Dinesh Pamunuwa of Engineering has been awarded the grant in partnership with Qimonda GBH of Germany (a world leader in Flash memory), CEA-LETI of France, Hyperstone of Germany (an SME specialising in controllers), and the Royal Institute of Technology (KTH) in Sweden.
The project tackles a very topical problem in Very Large Scale Integration (VLSI).
Next generation VLSI circuits can contain up to many billions of transistors and the design of these chips presents a number of challenges including power delivery and heat dissipation, interconnection problems and integration of disparate technologies. Many high-performance electronic designs also suffer from what is known as the memory bottleneck, with long and narrow wires providing slow access to off-chip memory banks.
Some of these difficulties can be addressed by having more than one active layer of transistors, so that the average wiring length is reduced, and different technologies - such as CMOS (digital transistors), FLASH (the high capacity memory technology used for example in pen drives), RF (Radio-Frequency) technology, and MEMS (Micro-Electro-Mechanical Systems) – can be integrated into a single chip more easily.
Such complex single-chip solutions are sought after to continue to deliver the functionality that electronics consumers have come to expect, and 3-D integration is being researched by many leading electronics companies, including processor companies such as Intel and IBM, as well as memory companies such as Samsung, Toshiba and Sandisk.
The award has been made under the EC’s FP7 programme. 'Framework programmes' (FPs) have been the main financial tools through which the European Union supports research and development activities covering almost all scientific disciplines.
The award will fund a research assistant and a PhD studentship over three years, as well as providing funds for close interaction with the other partners. The 3-D integration option to be explored in this project is Through-Silicon Via technology, one of the most aggressive integration technologies promising both high density and high performance. The project has already started, and the planned outcomes are three-fold: comprehensive simulation models, an FPGA prototype and a Si prototype.